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C/C++ Source or Header  |  1992-09-11  |  33KB  |  586 lines
  1. /* This file has been modified by Data General Corporation, November 1989. */
  2.  
  3.  
  4. /*
  5. *            Disassembler Instruction Table
  6. *
  7. *    The first field of the table is the opcode field. If an opcode
  8. *    is specified which has any non-opcode bits on, a system error
  9. *    will occur when the system attempts the install it into the
  10. *    instruction table.  The second parameter is a pointer to the
  11. *    instruction mnemonic. Each operand is specified by offset, width,
  12. *    and type. The offset is the bit number of the least significant
  13. *    bit of the operand with bit 0 being the least significant bit of
  14. *    the instruction. The width is the number of bits used to specify
  15. *    the operand. The type specifies the output format to be used for
  16. *    the operand. The valid formats are: register, register indirect,
  17. *    hex constant, and bit field specification.  The last field is a
  18. *    pointer to the next instruction in the linked list.  These pointers
  19. *    are initialized by init_disasm().
  20. *
  21. *                Structure Format
  22. *
  23. *       struct INSTAB {
  24. *          UPINT opcode;
  25. *          char *mnemonic;
  26. *          struct OPSPEC op1,op2,op3;
  27. *          struct SIM_FLAGS flgs;
  28. *          struct INSTAB *next;
  29. *       }
  30. *
  31. *       struct OPSPEC {
  32. *          UPINT offset:5;
  33. *          UPINT width:6;
  34. *          UPINT type:5;
  35. *       }
  36. *
  37. *                Revision History
  38. *
  39. *    Revision 1.0    11/08/85    Creation date
  40. *         1.1    02/05/86    Updated instruction mnemonic table MD
  41. *         1.2    06/16/86    Updated SIM_FLAGS for floating point
  42. *         1.3    09/20/86    Updated for new encoding
  43. *             05/11/89    R. Trawick adapted from Motorola disassembler
  44. */
  45.  
  46. #include <stdio.h>
  47.  
  48.  
  49. /*
  50.  * This file contains the structures and constants needed to build the M88000
  51.  * simulator.  It is the main include file, containing all the
  52.  * structures, macros and definitions except for the floating point
  53.  * instruction set.
  54.  */
  55.  
  56. /*
  57.  * The following flag informs the Simulator as to what type of byte ordering
  58.  * will be used. For instance, a BOFLAG = 1 indicates a DEC VAX and IBM type
  59.  * of ordering shall be used.
  60. */
  61.  
  62. /* # define     BOFLAG   1                       /* BYTE ORDERING FLAG */
  63.  
  64. /* define the number of bits in the primary opcode field of the instruction,
  65.  * the destination field, the source 1 and source 2 fields.
  66.  */
  67. # define    OP       8                        /* size of opcode field */ 
  68. # define    DEST     6                        /* size of destination  */
  69. # define    SOURCE1  6                        /* size of source1      */
  70. # define    SOURCE2  6                        /* size of source2      */
  71.  
  72. # define    REGs    32                        /* number of registers  */
  73.  
  74. # define    WORD    long
  75. # define    FLAG    unsigned
  76. # define    STATE   short 
  77.  
  78. # define    TRUE     1
  79. # define    FALSE    0
  80.  
  81. # define    READ     0
  82. # define    WRITE    1
  83.  
  84. /* The next four equates define the priorities that the various classes
  85.  * of instructions have regarding writing results back into registers and
  86.  * signalling exceptions.
  87.  */
  88.  
  89. # define    PINT  0   /* Integer Priority */
  90. # define    PFLT  1   /* Floating Point Priority */
  91. # define    PMEM  2   /* Memory Priority */
  92. # define    NA    3   /* Not Applicable, instruction doesnt write to regs */
  93. # define    HIPRI 3   /* highest of these priorities */
  94.  
  95. /* The instruction registers are an artificial mechanism to speed up
  96.  * simulator execution.  In the real processor, an instruction register
  97.  * is 32 bits wide.  In the simulator, the 32 bit instruction is kept in
  98.  * a structure field called rawop, and the instruction is partially decoded,
  99.  * and split into various fields and flags which make up the other fields
  100.  * of the structure.
  101.  * The partial decode is done when the instructions are initially loaded
  102.  * into simulator memory.  The simulator code memory is not an array of
  103.  * 32 bit words, but is an array of instruction register structures.
  104.  * Yes this wastes memory, but it executes much quicker.
  105.  */
  106.  
  107. struct IR_FIELDS {
  108.             unsigned long   op:OP,
  109.                     dest: DEST,
  110.                     src1: SOURCE1,
  111.                     src2: SOURCE2;
  112.                   int   ltncy,
  113.                     extime,
  114.                     wb_pri;     /* writeback priority     */
  115.             unsigned short  imm_flags:2,/* immediate size         */
  116.                     rs1_used:1, /* register source 1 used */
  117.                     rs2_used:1, /* register source 2 used */
  118.                     rsd_used:1, /* register source/dest. used */
  119.                     c_flag:1,   /* complement      */
  120.                     u_flag:1,   /* upper half word */
  121.                     n_flag:1,   /* execute next    */
  122.                     wb_flag:1,  /* uses writeback slot */
  123.                     dest_64:1,  /* dest size       */
  124.                     s1_64:1,    /* source 1 size   */
  125.                     s2_64:1,    /* source 2 size   */
  126.                     scale_flag:1, /* scaled register */
  127.                     brk_flg:1;
  128.                  };
  129.  
  130. struct    mem_segs {
  131.     struct mem_wrd *seg;            /* pointer (returned by calloc) to segment */
  132.     unsigned long baseaddr;            /* base load address from file headers */
  133.     unsigned long endaddr;            /* Ending address of segment */
  134.     int          flags;            /* segment control flags (none defined 12/5/86) */
  135. };
  136.  
  137. #define    MAXSEGS        (10)            /* max number of segment allowed */
  138. #define    MEMSEGSIZE    (sizeof(struct mem_segs))/* size of mem_segs structure */
  139.  
  140.  
  141. #define BRK_RD        (0x01)            /* break on memory read */
  142. #define BRK_WR        (0x02)            /* break on memory write */
  143. #define BRK_EXEC    (0x04)            /* break on execution */
  144. #define    BRK_CNT        (0x08)            /* break on terminal count */
  145.  
  146.  
  147. struct    mem_wrd {
  148.     struct IR_FIELDS opcode;        /* simulator instruction break down */
  149.     union {
  150.         unsigned long  l;        /* memory element break down */
  151.         unsigned short s[2];
  152.         unsigned char  c[4];
  153.     } mem;
  154. };
  155.  
  156. #define    MEMWRDSIZE    (sizeof(struct mem_wrd))    /* size of each 32 bit memory model */
  157.  
  158. /* External declarations */
  159.  
  160. extern    struct mem_segs memory[];
  161. extern    struct PROCESSOR m78000;
  162.  
  163. struct  PROCESSOR   {
  164.          unsigned WORD
  165.                 ip,          /* execute instruction pointer */
  166.                 vbr,         /* vector base register */
  167.                 psr;         /* processor status register */
  168.  
  169.             WORD    S1bus, /* source 1 */
  170.                             S2bus, /* source 2 */
  171.                             Dbus,  /* destination */
  172.                 DAbus, /* data address bus */
  173.                             ALU,
  174.                 Regs[REGs],       /* data registers */
  175.                 time_left[REGs],  /* max clocks before reg is available */
  176.                 wb_pri[REGs],     /* writeback priority of reg */
  177.                 SFU0_regs[REGs],  /* integer unit control regs */
  178.                 SFU1_regs[REGs],  /* floating point control regs */
  179.                 Scoreboard[REGs],
  180.                 Vbr;
  181.         unsigned WORD   scoreboard,
  182.                 Psw,
  183.                 Tpsw;
  184.             FLAG   jump_pending:1;   /* waiting for a jump instr. */
  185.                     };
  186.  
  187. # define    i26bit      1    /* size of immediate field */
  188. # define    i16bit      2
  189. # define    i10bit      3
  190.  
  191. /* Definitions for fields in psr */
  192.  
  193. # define mode  31
  194. # define rbo   30
  195. # define ser   29
  196. # define carry 28
  197. # define sf7m  11
  198. # define sf6m  10
  199. # define sf5m   9
  200. # define sf4m   8
  201. # define sf3m   7
  202. # define sf2m   6
  203. # define sf1m   5
  204. # define mam    4
  205. # define inm    3
  206. # define exm    2
  207. # define trm    1
  208. # define ovfm   0
  209.  
  210. #define        MODEMASK   (1<<(mode-1))
  211. # define    SILENT     0   /* simulate without output to crt */
  212. # define    VERBOSE    1   /* simulate in verbose mode */
  213. # define    PR_INSTR   2   /* only print instructions */
  214.  
  215. # define    RESET      16 /* reset phase */
  216.  
  217. # define    PHASE1     0  /* data path phases */
  218. # define    PHASE2     1
  219.  
  220. /* the 1 clock operations */
  221.  
  222. # define    ADDU        1
  223. # define    ADDC        2
  224. # define    ADDUC       3
  225. # define    ADD         4
  226.  
  227. # define    SUBU    ADD+1
  228. # define    SUBB    ADD+2
  229. # define    SUBUB   ADD+3
  230. # define    SUB     ADD+4
  231.  
  232. # define    AND     ADD+5
  233. # define    OR      ADD+6
  234. # define    XOR     ADD+7
  235. # define    CMP     ADD+8
  236.                         
  237. /* the LOADS */
  238.  
  239. # define    LDAB    CMP+1
  240. # define    LDAH    CMP+2
  241. # define    LDA     CMP+3
  242. # define    LDAD    CMP+4
  243.  
  244. # define    LDB   LDAD+1
  245. # define    LDH   LDAD+2
  246. # define    LD    LDAD+3
  247. # define    LDD   LDAD+4
  248. # define    LDBU  LDAD+5
  249. # define    LDHU  LDAD+6
  250.  
  251. /* the STORES */
  252.  
  253. # define    STB    LDHU+1
  254. # define    STH    LDHU+2
  255. # define    ST     LDHU+3
  256. # define    STD    LDHU+4
  257.  
  258. /* the exchange */
  259.  
  260. # define    XMEMBU LDHU+5
  261. # define    XMEM   LDHU+6
  262.  
  263. /* the branches */
  264. # define    JSR    STD+1
  265. # define    BSR    STD+2
  266. # define    BR     STD+3
  267. # define    JMP    STD+4
  268. # define    BB1    STD+5
  269. # define    BB0    STD+6
  270. # define    RTN    STD+7
  271. # define    BCND   STD+8
  272.  
  273. /* the TRAPS */
  274. # define    TB1    BCND+1
  275. # define    TB0    BCND+2
  276. # define    TCND   BCND+3
  277. # define    RTE    BCND+4
  278. # define    TBND   BCND+5
  279.  
  280. /* the MISC instructions */
  281. # define    MUL     TBND + 1
  282. # define    DIV     MUL  +2
  283. # define    DIVU    MUL  +3
  284. # define    MASK    MUL  +4
  285. # define    FF0     MUL  +5
  286. # define    FF1     MUL  +6
  287. # define    CLR     MUL  +7
  288. # define    SET     MUL  +8
  289. # define    EXT     MUL  +9
  290. # define    EXTU    MUL  +10
  291. # define    MAK     MUL  +11
  292. # define    ROT     MUL  +12
  293.  
  294. /* control register manipulations */
  295.  
  296. # define    LDCR    ROT  +1
  297. # define    STCR    ROT  +2
  298. # define    XCR     ROT  +3
  299.  
  300. # define    FLDCR    ROT  +4
  301. # define    FSTCR    ROT  +5
  302. # define    FXCR     ROT  +6
  303.  
  304.  
  305. # define    NOP     XCR +1
  306.  
  307. /* floating point instructions */
  308.  
  309. # define    FADD    NOP +1
  310. # define    FSUB    NOP +2
  311. # define    FMUL    NOP +3
  312. # define    FDIV    NOP +4
  313. # define    FSQRT   NOP +5
  314. # define    FCMP    NOP +6
  315. # define    FIP     NOP +7
  316. # define    FLT     NOP +8
  317. # define    INT     NOP +9
  318. # define    NINT    NOP +10
  319. # define    TRNC    NOP +11
  320. # define    FLDC   NOP +12
  321. # define    FSTC   NOP +13
  322. # define    FXC    NOP +14
  323.  
  324. # define UEXT(src,off,wid) ((((unsigned int)(src))>>(off)) & ((1<<(wid)) - 1))
  325. # define SEXT(src,off,wid) (((((int)(src))<<(32-((off)+(wid)))) >>(32-(wid))) )
  326. # define MAKE(src,off,wid) \
  327.   ((((unsigned int)(src)) & ((1<<(wid)) - 1)) << (off))
  328.  
  329. # define opword(n) (unsigned long) (memaddr->mem.l)
  330.  
  331. /*  Constants and Masks */
  332.  
  333. #define SFU0       0x80000000
  334. #define SFU1       0x84000000
  335. #define SFU7       0x9c000000
  336. #define RRI10      0xf0000000
  337. #define RRR        0xf4000000
  338. #define SFUMASK    0xfc00ffe0
  339. #define RRRMASK    0xfc00ffe0
  340. #define RRI10MASK  0xfc00fc00
  341. #define DEFMASK    0xfc000000
  342. #define CTRL       0x0000f000
  343. #define CTRLMASK   0xfc00f800
  344.  
  345. /* Operands types */
  346.  
  347. #define HEX          1
  348. #define REG          2
  349. #define IND          3
  350. #define CONT         3
  351. #define IND          3
  352. #define BF           4
  353. #define REGSC        5    /* scaled register */
  354. #define CRREG        6    /* control register */
  355. #define FCRREG       7    /* floating point control register */
  356. #define PCREL         8
  357. #define CONDMASK     9
  358.  
  359. /* Hashing Specification */
  360.  
  361. #define HASHVAL     79
  362.  
  363. /* Type definitions */
  364.  
  365. typedef unsigned int UINT;
  366.  
  367. /* Structure templates */
  368.  
  369. typedef struct {
  370.    unsigned int offset:5;
  371.    unsigned int width:6;
  372.    unsigned int type:5;
  373. } OPSPEC;
  374.  
  375.     struct SIM_FLAGS {
  376.           int  ltncy,   /* latency (max number of clocks needed to execute) */
  377.           extime,   /* execution time (min number of clocks needed to execute) */
  378.           wb_pri;   /* writeback slot priority */
  379.    unsigned long   op:OP,   /* simulator version of opcode */
  380.          imm_flags:2,   /* 10,16 or 26 bit immediate flags */
  381.           rs1_used:1,   /* register source 1 used */
  382.           rs2_used:1,   /* register source 2 used */
  383.           rsd_used:1,   /* register source/dest used */
  384.         c_flag:1,   /* complement */
  385.         u_flag:1,   /* upper half word */
  386.         n_flag:1,   /* execute next */
  387.            wb_flag:1,   /* uses writeback slot */
  388.            dest_64:1,   /* double precision dest */
  389.          s1_64:1,   /* double precision source 1 */
  390.          s2_64:1,   /* double precision source 2 */
  391.         scale_flag:1;   /* register is scaled */
  392. };
  393.  
  394. typedef struct INSTRUCTAB {
  395.    unsigned int  opcode;
  396.    char          *mnemonic;
  397.    OPSPEC        op1,op2,op3;
  398.    struct SIM_FLAGS flgs;
  399.    struct INSTRUCTAB    *next;
  400. } INSTAB;
  401.  
  402.  
  403. /* Opcode     Mnemonic       Op 1 Spec     Op 2 Spec    Op 3 Spec         Simflags             Next  */
  404.  
  405. static INSTAB  instructions[] =
  406. {0xf400c800,"jsr      ",{0,5,REG}   ,{0,0,0}      ,{0,0,0}   , {2,2,NA,JSR ,          0,0,1,0,0,0,0,1,0,0,0,0}, NULL,
  407.  0xf400cc00,"jsr.n    ",{0,5,REG}   ,{0,0,0}      ,{0,0,0}   , {1,1,NA,JSR ,          0,0,1,0,0,0,1,1,0,0,0,0}, NULL,
  408.  0xf400c000,"jmp      ",{0,5,REG}   ,{0,0,0}      ,{0,0,0}   , {2,2,NA,JMP ,          0,0,1,0,0,0,0,1,0,0,0,0}, NULL,
  409.  0xf400c400,"jmp.n    ",{0,5,REG}   ,{0,0,0}      ,{0,0,0}   , {1,1,NA,JMP ,          0,0,1,0,0,0,1,1,0,0,0,0}, NULL,
  410.  0xc8000000,"bsr      ",{0,26,PCREL},{0,0,0}      ,{0,0,0}   , {2,2,NA,BSR ,     i26bit,0,0,0,0,0,0,1,0,0,0,0}, NULL,
  411.  0xcc000000,"bsr.n    ",{0,26,PCREL},{0,0,0}      ,{0,0,0}   , {1,1,NA,BSR ,     i26bit,0,0,0,0,0,1,1,0,0,0,0}, NULL,
  412.  0xc0000000,"br       ",{0,26,PCREL},{0,0,0}      ,{0,0,0}   , {2,2,NA,BR  ,     i26bit,0,0,0,0,0,0,1,0,0,0,0}, NULL,
  413.  0xc4000000,"br.n     ",{0,26,PCREL},{0,0,0}      ,{0,0,0}   , {1,1,NA,BR  ,     i26bit,0,0,0,0,0,1,1,0,0,0,0}, NULL,
  414.  0xd0000000,"bb0      ",{21,5,HEX}  ,{16,5,REG}   ,{0,16,PCREL},{2,2,NA,BB0,     i16bit,0,1,0,0,0,0,1,0,0,0,0}, NULL,
  415.  0xd4000000,"bb0.n    ",{21,5,HEX}  ,{16,5,REG}   ,{0,16,PCREL},{1,1,NA,BB0,     i16bit,0,1,0,0,0,1,1,0,0,0,0}, NULL,
  416.  0xd8000000,"bb1      ",{21,5,HEX},{16,5,REG}     ,{0,16,PCREL},{2,2,NA,BB1,     i16bit,0,1,0,0,0,0,1,0,0,0,0}, NULL,
  417.  0xdc000000,"bb1.n    ",{21,5,HEX},{16,5,REG}     ,{0,16,PCREL},{1,1,NA,BB1,     i16bit,0,1,0,0,0,1,1,0,0,0,0}, NULL,
  418.  0xf000d000,"tb0      ",{21,5,HEX}  ,{16,5,REG}   ,{0,10,HEX}, {2,2,NA,TB0 ,     i10bit,0,1,0,0,0,0,1,0,0,0,0}, NULL,
  419.  0xf000d800,"tb1      ",{21,5,HEX}  ,{16,5,REG}   ,{0,10,HEX}, {2,2,NA,TB1 ,     i10bit,0,1,0,0,0,0,1,0,0,0,0}, NULL,
  420.  0xe8000000,"bcnd     ",{21,5,CONDMASK},{16,5,REG},{0,16,PCREL},{2,2,NA,BCND,    i16bit,0,1,0,0,0,0,1,0,0,0,0}, NULL,
  421.  0xec000000,"bcnd.n   ",{21,5,CONDMASK},{16,5,REG},{0,16,PCREL},{1,1,NA,BCND,    i16bit,0,1,0,0,0,1,1,0,0,0,0}, NULL,
  422.  0xf000e800,"tcnd     ",{21,5,CONDMASK},{16,5,REG},{0,10,HEX}, {2,2,NA,TCND,     i10bit,0,1,0,0,0,0,1,0,0,0,0}, NULL,
  423.  0xf8000000,"tbnd     ",{16,5,REG}  ,{0,16,HEX}   ,{0,0,0}   , {2,2,NA,TBND,     i10bit,1,0,0,0,0,0,1,0,0,0,0}, NULL,
  424.  0xf400f800,"tbnd     ",{16,5,REG}  ,{0,5,REG}    ,{0,0,0}   , {2,2,NA,TBND,          0,1,1,0,0,0,0,1,0,0,0,0}, NULL,
  425.  0xf400fc00,"rte      ",{0,0,0}     ,{0,0,0}      ,{0,0,0}   , {2,2,NA,RTE ,          0,0,0,0,0,0,0,1,0,0,0,0}, NULL,
  426.  0x1c000000,"ld.b     ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {3,1,PMEM,LDB    ,i16bit,1,0,1,0,0,0,1,0,0,0,0}, NULL,
  427.  0xf4001c00,"ld.b     ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {3,1,PMEM,LDB     ,    0,1,1,1,0,0,0,1,0,0,0,0}, NULL,
  428.  0x0c000000,"ld.bu    ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {3,1,PMEM,LDBU,   i16bit,1,0,1,0,0,0,1,0,0,0,0}, NULL,
  429.  0xf4000c00,"ld.bu    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {3,1,PMEM,LDBU        ,0,1,1,1,0,0,0,1,0,0,0,0}, NULL,
  430.  0x18000000,"ld.h     ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {3,1,PMEM,LDH    ,i16bit,1,0,1,0,0,0,1,0,0,0,0}, NULL,
  431.  0xf4001800,"ld.h     ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {3,1,PMEM,LDH         ,0,1,1,1,0,0,0,1,0,0,0,0}, NULL,
  432.  0xf4001a00,"ld.h     ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REGSC},{3,1,PMEM,LDH         ,0,1,1,1,0,0,0,1,0,0,0,1}, NULL,
  433.  0x08000000,"ld.hu    ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {3,1,PMEM,LDHU,   i16bit,1,0,1,0,0,0,1,0,0,0,0}, NULL,
  434.  0xf4000800,"ld.hu    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {3,1,PMEM,LDHU        ,0,1,1,1,0,0,0,1,0,0,0,0}, NULL,
  435.  0xf4000a00,"ld.hu    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REGSC},{3,1,PMEM,LDHU        ,0,1,1,1,0,0,0,1,0,0,0,1}, NULL,
  436.  0x14000000,"ld       ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {3,1,PMEM,LD     ,i16bit,1,0,1,0,0,0,1,0,0,0,0}, NULL,
  437.  0xf4001400,"ld       ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {3,1,PMEM,LD          ,0,1,1,1,0,0,0,1,0,0,0,0}, NULL,
  438.  0xf4001600,"ld       ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REGSC},{3,1,PMEM,LD          ,0,1,1,1,0,0,0,1,0,0,0,1}, NULL,
  439.  0x10000000,"ld.d     ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {3,1,PMEM,LDD    ,i16bit,1,0,1,0,0,0,1,0,0,0,0}, NULL,
  440.  0xf4001000,"ld.d     ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {3,1,PMEM,LDD         ,0,1,1,1,0,0,0,1,0,0,0,0}, NULL,
  441.  0xf4001200,"ld.d     ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REGSC},{3,1,PMEM,LDD         ,0,1,1,1,0,0,0,1,0,0,0,1}, NULL,
  442.  0xf4001500,"ld.usr   ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {3,1,PMEM,LD          ,0,1,1,1,0,0,0,1,0,0,0,0}, NULL,
  443.  0xf4001700,"ld.usr   ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REGSC},{3,1,PMEM,LD          ,0,1,1,1,0,0,0,1,0,0,0,1}, NULL,
  444.  0x2c000000,"st.b     ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {1,1,NA,STB      ,i16bit,1,0,1,0,0,0,1,0,0,0,0}, NULL,
  445.  0xf4002c00,"st.b     ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,NA,STB           ,0,1,1,1,0,0,0,1,0,0,0,0}, NULL,
  446.  0x28000000,"st.h     ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {1,1,NA,STH      ,i16bit,1,0,1,0,0,0,1,0,0,0,0}, NULL,
  447.  0xf4002800,"st.h     ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,NA,STH           ,0,1,1,1,0,0,0,1,0,0,0,0}, NULL,
  448.  0xf4002a00,"st.h     ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REGSC},{1,1,NA,STH           ,0,1,1,1,0,0,0,1,0,0,0,1}, NULL,
  449.  0x24000000,"st       ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {1,1,NA,ST       ,i16bit,1,0,1,0,0,0,1,0,0,0,0}, NULL,
  450.  0xf4002400,"st       ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,NA,ST            ,0,1,1,1,0,0,0,1,0,0,0,0}   ,NULL,
  451.  0xf4002600,"st       ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REGSC},{1,1,NA,ST            ,0,1,1,1,0,0,0,1,0,0,0,1}   ,NULL,
  452.  0x20000000,"st.d     ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {1,1,NA,STD      ,i16bit,0,1,0,0,0,0,1,0,0,0,0}   ,NULL,
  453.  0xf4002000,"st.d     ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,NA,STD           ,0,1,1,1,0,0,0,1,0,0,0,0}   ,NULL,
  454.  0xf4002200,"st.d     ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REGSC},{1,1,NA,STD           ,0,1,1,1,0,0,0,1,0,0,0,1}   ,NULL,
  455.  0xf4002500,"st.usr   ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,NA,ST            ,0,1,1,1,0,0,0,1,0,0,0,0}   ,NULL,
  456.  0xf4002700,"st.usr   ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REGSC},{1,1,NA,ST            ,0,1,1,1,0,0,0,1,0,0,0,1}   ,NULL,
  457.  0x00000000,"xmem.bu  ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {3,1,PMEM,XMEMBU ,i16bit,1,1,1,0,0,0,1,0,0,0,0}   ,NULL,
  458.  0xf4000000,"xmem.bu  ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {3,1,PMEM,XMEM        ,0,1,1,1,0,0,0,1,0,0,0,0}   ,NULL,
  459.  0x04000000,"xmem     ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {3,1,PMEM,XMEM   ,i16bit,1,1,1,0,0,0,1,0,0,0,0}   ,NULL,
  460.  0xf4000400,"xmem     ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {3,1,PMEM,XMEM        ,0,1,1,1,0,0,0,1,0,0,0,0}   ,NULL,
  461.  0xf4000600,"xmem     ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REGSC},{3,1,PMEM,XMEM        ,0,1,1,1,0,0,0,1,0,0,0,1}   ,NULL,
  462.  0xf4000500,"xmem.usr ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {3,1,PMEM,XMEM        ,0,1,1,1,0,0,0,1,0,0,0,0}   ,NULL,
  463.  0xf4000700,"xmem.usr ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REGSC},{3,1,PMEM,XMEM        ,0,1,1,1,0,0,0,1,0,0,0,1}   ,NULL,
  464.  0xf4003e00,"lda.b    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REGSC},{1,1,PINT,LDAH,        0,1,1,1,0,0,0,0,0,0,0,1}   ,NULL,
  465.  0xf4003a00,"lda.h    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REGSC},{1,1,PINT,LDAH,        0,1,1,1,0,0,0,0,0,0,0,1}   ,NULL,
  466.  0xf4003600,"lda      ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REGSC},{1,1,PINT,LDA ,        0,1,1,1,0,0,0,0,0,0,0,1}   ,NULL,
  467.  0xf4003200,"lda.d    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REGSC},{1,1,PINT,LDAD,        0,1,1,1,0,0,0,0,0,0,0,1}   ,NULL,
  468.  
  469.  0x80004000,"ldcr     ",{21,5,REG}  ,{5,6,CRREG}  ,{0,0,0}    ,{1,1,PINT,LDCR,        0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL,
  470.  0x80008000,"stcr     ",{16,5,REG}  ,{5,6,CRREG}  ,{0,0,0}    ,{1,1,PINT,STCR,        0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL,
  471.  0x8000c000,"xcr      ",{21,5,REG}  ,{16,5,REG}   ,{5,6,CRREG},{1,1,PINT,XCR,         0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL,
  472.  
  473.  0xf4006000,"addu     ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,ADDU,        0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL,
  474.  0xf4006200,"addu.ci  ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,ADDU,        0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL,
  475.  0xf4006100,"addu.co  ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,ADDU,        0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL,
  476.  0xf4006300,"addu.cio ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,ADDU,        0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL,
  477.  0xf4006400,"subu     ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,SUBU,        0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL,
  478.  0xf4006600,"subu.ci  ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,SUBU,        0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL,
  479.  0xf4006500,"subu.co  ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,SUBU,        0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL,
  480.  0xf4006700,"subu.cio ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,SUBU,        0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL,
  481.  0xf4006900,"divu     ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {32,32,PINT,DIVU,        0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL,
  482.  0xf4006d00,"mul      ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,4,PINT,MUL,      0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL,
  483.  0xf4007000,"add      ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,ADD ,        0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL,
  484.  0xf4007200,"add.ci   ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,ADD ,        0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL,
  485.  0xf4007100,"add.co   ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,ADD ,        0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL,
  486.  0xf4007300,"add.cio  ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,ADD ,        0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL,
  487.  0xf4007400,"sub      ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,SUB ,        0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL,
  488.  0xf4007600,"sub.ci   ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,SUB ,        0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL,
  489.  0xf4007500,"sub.co   ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,SUB ,        0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL,
  490.  0xf4007700,"sub.cio  ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,SUB ,        0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL,
  491.  0xf4007900,"div      ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {32,32,PINT,DIV ,      0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL,
  492.  0xf4007d00,"cmp      ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,CMP,         0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL,
  493.  
  494.  0x60000000,"addu     ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {1,1,PINT,ADDU,   i16bit,1,0,1,0,0,0,0,0,0,0,0}   ,NULL,
  495.  0x64000000,"subu     ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {1,1,PINT,SUBU,   i16bit,1,0,1,0,0,0,0,0,0,0,0}   ,NULL,
  496.  
  497.  0x68000000,"divu     ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {32,32,PINT,DIVU, i16bit,1,0,1,0,0,0,0,0,0,0,0}   ,NULL,
  498.  0x6c000000,"mul      ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {4,1,PINT,MUL,    i16bit,1,0,1,0,0,0,0,0,0,0,0}   ,NULL,
  499.  0x70000000,"add      ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {1,1,PINT,ADD,    i16bit,1,0,1,0,0,0,0,0,0,0,0}   ,NULL,
  500.  0x74000000,"sub      ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {1,1,PINT,SUB,    i16bit,1,0,1,0,0,0,0,0,0,0,0}   ,NULL,
  501.  0x78000000,"div      ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {32,32,PINT,DIV,  i16bit,1,0,1,0,0,0,0,0,0,0,0}   ,NULL,
  502.  0x7c000000,"cmp      ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {1,1,PINT,CMP,    i16bit,1,0,1,0,0,0,0,0,0,0,0}   ,NULL,
  503.  
  504.  0xf4004000,"and      ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,AND         ,0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL,
  505.  0xf4004400,"and.c    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,AND         ,0,1,1,1,1,0,0,0,0,0,0,0}   ,NULL,
  506.  0xf4005800,"or       ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,OR          ,0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL,
  507.  0xf4005c00,"or.c     ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,OR          ,0,1,1,1,1,0,0,0,0,0,0,0}   ,NULL,
  508.  0xf4005000,"xor      ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,XOR         ,0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL,
  509.  0xf4005400,"xor.c    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,XOR         ,0,1,1,1,1,0,0,0,0,0,0,0}   ,NULL,
  510.  0x40000000,"and      ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {1,1,PINT,AND    ,i16bit,1,0,1,0,0,0,0,0,0,0,0}   ,NULL,
  511.  0x44000000,"and.u    ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {1,1,PINT,AND    ,i16bit,1,0,1,0,1,0,0,0,0,0,0}   ,NULL,
  512.  0x58000000,"or       ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {1,1,PINT,OR     ,i16bit,1,0,1,0,0,0,0,0,0,0,0}   ,NULL,
  513.  0x5c000000,"or.u     ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {1,1,PINT,OR     ,i16bit,1,0,1,0,1,0,0,0,0,0,0}   ,NULL,
  514.  0x50000000,"xor      ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {1,1,PINT,XOR    ,i16bit,1,0,1,0,0,0,0,0,0,0,0}   ,NULL,
  515.  0x54000000,"xor.u    ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {1,1,PINT,XOR    ,i16bit,1,0,1,0,1,0,0,0,0,0,0}   ,NULL,
  516.  0x48000000,"mask     ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {1,1,PINT,MASK   ,i16bit,1,0,1,0,0,0,0,0,0,0,0}   ,NULL,
  517.  0x4c000000,"mask.u   ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {1,1,PINT,MASK   ,i16bit,1,0,1,0,1,0,0,0,0,0,0}   ,NULL,
  518.  0xf400ec00,"ff0      ",{21,5,REG}  ,{0,5,REG}    ,{0,0,0}   , {1,1,PINT,FF0         ,0,0,1,1,0,0,0,0,0,0,0,0}   ,NULL,
  519.  0xf400e800,"ff1      ",{21,5,REG}  ,{0,5,REG}    ,{0,0,0}   , {1,1,PINT,FF1         ,0,0,1,1,0,0,0,0,0,0,0,0}   ,NULL,
  520.  0xf0008000,"clr      ",{21,5,REG}  ,{16,5,REG}   ,{0,10,BF} , {1,1,PINT,CLR    ,i10bit,1,0,1,0,0,0,0,0,0,0,0}   ,NULL,
  521.  0xf0008800,"set      ",{21,5,REG}  ,{16,5,REG}   ,{0,10,BF} , {1,1,PINT,SET    ,i10bit,1,0,1,0,0,0,0,0,0,0,0}   ,NULL,
  522.  0xf0009000,"ext      ",{21,5,REG}  ,{16,5,REG}   ,{0,10,BF} , {1,1,PINT,EXT    ,i10bit,1,0,1,0,0,0,0,0,0,0,0}   ,NULL,
  523.  0xf0009800,"extu     ",{21,5,REG}  ,{16,5,REG}   ,{0,10,BF} , {1,1,PINT,EXTU   ,i10bit,1,0,1,0,0,0,0,0,0,0,0}   ,NULL,
  524.  0xf000a000,"mak      ",{21,5,REG}  ,{16,5,REG}   ,{0,10,BF} , {1,1,PINT,MAK    ,i10bit,1,0,1,0,0,0,0,0,0,0,0}   ,NULL,
  525.  0xf000a800,"rot      ",{21,5,REG}  ,{16,5,REG}   ,{0,10,BF} , {1,1,PINT,ROT    ,i10bit,1,0,1,0,0,0,0,0,0,0,0}   ,NULL,
  526.  0xf4008000,"clr      ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,CLR         ,0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL,
  527.  0xf4008800,"set      ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,SET         ,0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL,
  528.  0xf4009000,"ext      ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,EXT         ,0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL,
  529.  0xf4009800,"extu     ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,EXTU        ,0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL,
  530.  0xf400a000,"mak      ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,MAK         ,0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL,
  531.  0xf400a800,"rot      ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,ROT         ,0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL,
  532.  
  533.  0x84002800,"fadd.sss ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {5,1,PFLT,FADD        ,0,1,1,1,0,0,0,1,0,0,0,0}   ,NULL,
  534.  0x84002880,"fadd.ssd ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {6,2,PFLT,FADD        ,0,1,1,1,0,0,0,1,0,0,1,0}   ,NULL,
  535.  0x84002a00,"fadd.sds ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {6,2,PFLT,FADD        ,0,1,1,1,0,0,0,1,0,1,0,0}   ,NULL,
  536.  0x84002a80,"fadd.sdd ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {6,2,PFLT,FADD        ,0,1,1,1,0,0,0,1,0,1,1,0}   ,NULL,
  537.  0x84002820,"fadd.dss ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {6,2,PFLT,FADD        ,0,1,1,1,0,0,0,1,1,0,0,0}   ,NULL,
  538.  0x840028a0,"fadd.dsd ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {6,2,PFLT,FADD        ,0,1,1,1,0,0,0,1,1,0,1,0}   ,NULL,
  539.  0x84002a20,"fadd.dds ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {6,2,PFLT,FADD        ,0,1,1,1,0,0,0,1,1,1,0,0}   ,NULL,
  540.  0x84002aa0,"fadd.ddd ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {6,2,PFLT,FADD        ,0,1,1,1,0,0,0,1,1,1,1,0}   ,NULL,
  541.  0x84003000,"fsub.sss ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {5,1,PFLT,FSUB        ,0,1,1,1,0,0,0,1,0,0,0,0}   ,NULL,
  542.  0x84003080,"fsub.ssd ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {6,2,PFLT,FSUB        ,0,1,1,1,0,0,0,1,0,0,1,0}   ,NULL,
  543.  0x84003200,"fsub.sds ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {6,2,PFLT,FSUB        ,0,1,1,1,0,0,0,1,0,1,0,0}   ,NULL,
  544.  0x84003280,"fsub.sdd ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {6,2,PFLT,FSUB        ,0,1,1,1,0,0,0,1,0,1,1,0}   ,NULL,
  545.  0x84003020,"fsub.dss ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {6,2,PFLT,FSUB        ,0,1,1,1,0,0,0,1,1,0,0,0}   ,NULL,
  546.  0x840030a0,"fsub.dsd ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {6,2,PFLT,FSUB        ,0,1,1,1,0,0,0,1,1,0,1,0}   ,NULL,
  547.  0x84003220,"fsub.dds ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {6,2,PFLT,FSUB        ,0,1,1,1,0,0,0,1,1,1,0,0}   ,NULL,
  548.  0x840032a0,"fsub.ddd ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {6,2,PFLT,FSUB        ,0,1,1,1,0,0,0,1,1,1,1,0}   ,NULL,
  549.  0x84000000,"fmul.sss ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {6,1,PFLT,FMUL        ,0,1,1,1,0,0,0,1,0,0,0,0}   ,NULL,
  550.  0x84000080,"fmul.ssd ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {9,2,PFLT,FMUL        ,0,1,1,1,0,0,0,1,0,0,1,0}   ,NULL,
  551.  0x84000200,"fmul.sds ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {9,2,PFLT,FMUL        ,0,1,1,1,0,0,0,1,0,1,0,0}   ,NULL,
  552.  0x84000280,"fmul.sdd ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {9,2,PFLT,FMUL        ,0,1,1,1,0,0,0,1,0,1,1,0}   ,NULL,
  553.  0x84000020,"fmul.dss ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {9,2,PFLT,FMUL        ,0,1,1,1,0,0,0,1,1,0,0,0}   ,NULL,
  554.  0x840000a0,"fmul.dsd ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {9,2,PFLT,FMUL        ,0,1,1,1,0,0,0,1,1,0,1,0}   ,NULL,
  555.  0x84000220,"fmul.dds ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {9,2,PFLT,FMUL        ,0,1,1,1,0,0,0,1,1,1,0,0}   ,NULL,
  556.  0x840002a0,"fmul.ddd ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {9,2,PFLT,FMUL        ,0,1,1,1,0,0,0,1,1,1,1,0}   ,NULL,
  557.  0x84007000,"fdiv.sss ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {30,30,PFLT,FDIV      ,0,1,1,1,0,0,0,1,0,0,0,0}   ,NULL,
  558.  0x84007080,"fdiv.ssd ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {60,60,PFLT,FDIV      ,0,1,1,1,0,0,0,1,0,0,1,0}   ,NULL,
  559.  0x84007200,"fdiv.sds ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {60,60,PFLT,FDIV      ,0,1,1,1,0,0,0,1,0,1,0,0}   ,NULL,
  560.  0x84007280,"fdiv.sdd ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {60,60,PFLT,FDIV      ,0,1,1,1,0,0,0,1,0,1,1,0}   ,NULL,
  561.  0x84007020,"fdiv.dss ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {60,60,PFLT,FDIV      ,0,1,1,1,0,0,0,1,1,0,0,0}   ,NULL,
  562.  0x840070a0,"fdiv.dsd ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {60,60,PFLT,FDIV      ,0,1,1,1,0,0,0,1,1,0,1,0}   ,NULL,
  563.  0x84007220,"fdiv.dds ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {60,60,PFLT,FDIV      ,0,1,1,1,0,0,0,1,1,1,0,0}   ,NULL,
  564.  0x840072a0,"fdiv.ddd ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {60,60,PFLT,FDIV      ,0,1,1,1,0,0,0,1,1,1,1,0}   ,NULL,
  565.  0x84007800,"fsqrt.ss ",{21,5,REG}  ,{0,5,REG}    ,{0,0,0}   , {5,1,PFLT,FLT         ,0,0,1,1,0,0,0,1,0,0,0,0}   ,NULL,
  566.  0x84007880,"fsqrt.sd ",{21,5,REG}  ,{0,5,REG}    ,{0,0,0}   , {5,1,PFLT,FLT         ,0,0,1,1,0,0,0,1,0,0,0,0}   ,NULL,
  567.  0x84007820,"fsqrt.ds ",{21,5,REG}  ,{0,5,REG}    ,{0,0,0}   , {5,1,PFLT,FLT         ,0,0,1,1,0,0,0,1,0,0,0,0}   ,NULL,
  568.  0x840078a0,"fsqrt.dd ",{21,5,REG}  ,{0,5,REG}    ,{0,0,0}   , {6,1,PFLT,FLT         ,0,0,1,1,0,0,0,1,1,0,0,0}   ,NULL,
  569.  0x84003800,"fcmp.ss  ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {5,1,PFLT,FCMP        ,0,1,1,1,0,0,0,1,0,0,0,0}   ,NULL,
  570.  0x84003880,"fcmp.sd  ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {6,1,PFLT,FCMP        ,0,1,1,1,0,0,0,1,0,1,0,0}   ,NULL,
  571.  0x84003a00,"fcmp.ds  ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {6,1,PFLT,FCMP        ,0,1,1,1,0,0,0,1,1,0,0,0}   ,NULL,
  572.  0x84003a80,"fcmp.dd  ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {6,1,PFLT,FCMP        ,0,1,1,1,0,0,0,1,1,1,0,0}   ,NULL,
  573.  0x84002000,"flt.s    ",{21,5,REG}  ,{0,5,REG}    ,{0,0,0}   , {5,1,PFLT,FLT         ,0,0,1,1,0,0,0,1,0,0,0,0}   ,NULL,
  574.  0x84002020,"flt.d    ",{21,5,REG}  ,{0,5,REG}    ,{0,0,0}   , {6,1,PFLT,FLT         ,0,0,1,1,0,0,0,1,1,0,0,0}   ,NULL,
  575.  0x84004800,"int.s    ",{21,5,REG}  ,{0,5,REG}    ,{0,0,0}   , {5,1,PFLT,INT         ,0,0,1,1,0,0,0,1,0,0,0,0}   ,NULL,
  576.  0x84004880,"int.d    ",{21,5,REG}  ,{0,5,REG}    ,{0,0,0}   , {6,1,PFLT,INT         ,0,0,1,1,0,0,0,1,1,0,0,0}   ,NULL,
  577.  0x84005000,"nint.s   ",{21,5,REG}  ,{0,5,REG}    ,{0,0,0}   , {5,1,PFLT,INT         ,0,0,1,1,0,0,0,1,0,0,0,0}   ,NULL,
  578.  0x84005080,"nint.d   ",{21,5,REG}  ,{0,5,REG}    ,{0,0,0}   , {6,1,PFLT,INT         ,0,0,1,1,0,0,0,1,1,0,0,0}   ,NULL,
  579.  0x84005800,"trnc.s   ",{21,5,REG}  ,{0,5,REG}    ,{0,0,0}   , {5,1,PFLT,TRNC        ,0,0,1,1,0,0,0,1,0,0,0,0}   ,NULL,
  580.  0x84005880,"trnc.d   ",{21,5,REG}  ,{0,5,REG}    ,{0,0,0}   , {6,1,PFLT,TRNC        ,0,0,1,1,0,0,0,1,1,0,0,0}   ,NULL,
  581.  
  582.  0x80004800,"fldcr    ",{21,5,REG}  ,{5,6,FCRREG} ,{0,0,0}   , {1,1,PFLT,FLDC        ,0,0,1,1,0,0,0,1,0,0,0,0}   ,NULL,
  583.  0x80008800,"fstcr    ",{16,5,REG}  ,{5,6,FCRREG} ,{0,0,0}   , {1,1,PFLT,FSTC        ,0,0,1,1,0,0,0,1,0,0,0,0}   ,NULL,
  584.  0x8000c800,"fxcr     ",{21,5,REG}  ,{16,5,REG}   ,{5,6,FCRREG} , {1,1,PFLT,FXC         ,0,0,1,1,0,0,0,1,0,0,0,0}   ,NULL};
  585.  
  586.